In deep sub-micron integrated circuit technology, an embedded static random access memory (SRAM) device has become a popular storage unit of high speed communication, image processing and system-on-chip (SOC) products. The amount of embedded SRAM in microprocessors and SOCs increases to meet the performance requirement in each new technology generation. As silicon technology continues to scale from one generation to the next, the impact of intrinsic threshold voltage (Vt) variations in minimum geometry size bulk planar transistors reduces the complimentary metal-oxide-semiconductor (CMOS) SRAM cell static noise margin (SNM). This reduction in SNM caused by increasingly smaller transistor geometries is undesirable. SNM is further reduced when Vcc is scaled to a lower voltage.
To solve SRAM issues and to improve cell shrink capability, fin field effect transistor (FinFET) devices are often considered for some applications. The FinFET provides both speed and device stability. The FinFET has a channel (referred to as a fin channel) associated with a top surface and opposite sidewalls. Benefits can be derived from the additional sidewall device width (Ion performance) as well as better short channel control (sub-threshold leakage). Therefore, FinFETs are expected to have advantages in terms of gate length scaling and intrinsic Vt fluctuation. However, existing FinFET SRAM devices still have shortcomings, for example shortcomings related to small process margins between source/drain contacts and/or contact landing on fin structures. In addition, as FinFET SRAM cell sizes shrink, undesirable bridging may occur. These problems could adversely impact FinFET SRAM performance and/or reliability.
Therefore, although existing FinFET SRAM devices have been generally adequate for their intended purposes, they have not been entirely satisfactory in every aspect.